Luca Cassano received his Bachelor's degree and Master's degree in Computer Engineering in 2006 and 2009 respectively from the University of Pisa, Italy. In 2013 he received the Ph.D. in Information Engineering from the Department of Information Engineering of the University of Pisa, Italy. During his Ph.D. course I spent a visiting period at the Department of Automation and Informatics of the Politecnico di Torino, Italy, under the supervision of Professor Luca Sterpone, and a visiting period at the Cognitive Interaction Technology - Center of Excellence (CITEC) of the University of Bielefeld, Germany, under the supervision of Professor Mario Porrmann. He is currently a post doctoral research fellow at the Dipartimento di Elettronica, Informazione e Bioingegneria of the Politecnico di Milano, Italy, under the supervision of Professor Cristiana Bolchini. With his Ph.D. thesis, titled "Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs", he won the European semi-finals of the TTTC's E. J. McCluskey Doctoral Thesis Award held during ETS2014, in Paderborn, Germany, on May 26-30 2014, and he was the runner-up at the Award finals held during ITC2014, in Seattle, USA, on November 21-23 2014. His research activity is mainly focused on fault simulation, automatic test pattern generation, untestability analysis and fault diagnosis of digital circuits and systems, but he is also interested on the use of formal methods for digital system verification and on energy analysis of automatic weather stations.