NECSTFridayTalk – Past, Present and Future of Designing, Integrating and Simulating RTL Models
Speaker: Guillem López-Paradís
PhD Student, Barcelona Supercomputing Center
DEIB - NECSTLab Meeting Room (Bld. 20)
Online by Zoom
March 28th, 2025 | 11.30 am
Contact: Prof. Marco Santambrogio
PhD Student, Barcelona Supercomputing Center
DEIB - NECSTLab Meeting Room (Bld. 20)
Online by Zoom
March 28th, 2025 | 11.30 am
Contact: Prof. Marco Santambrogio
Sommario
On March 28th, 2025 at 11.30 am a new appointment of #NECSTFridayTalk series titled "Past, Present and Future of Designing, Integrating and Simulating RTL Models" will take place at DEIB NECSTLab Meeting Room (Building 20) and on line by Zoom.
During this talk, we will have, as speaker, Guillem López-Paradís, PhD Student at Barcelona Supercomputing Center.
In recent years, there has been a surge of interest in designing custom accelerators within heterogeneous system-on-chip (SoC) architectures. However, available tools to simulate low-level RTL designs often overlook the specific target system in which the design will operate. This hinders proper testing and debugging of functionalities, and does not allow co-designing the accelerator to obtain a balanced and efficient architecture. Furthermore, since the popularization of multiprocessors in the last few decades, which currently offer up to hundreds of cores per chip, it has become the norm to parallelize any software to obtain the maximum performance. However, if we look into the software tools needed to develop hardware, e.g., RTL simulators, we only see little adoption of parallel techniques, typically constrained to a single node and a few threads.
During this talk, we will have, as speaker, Guillem López-Paradís, PhD Student at Barcelona Supercomputing Center.
In recent years, there has been a surge of interest in designing custom accelerators within heterogeneous system-on-chip (SoC) architectures. However, available tools to simulate low-level RTL designs often overlook the specific target system in which the design will operate. This hinders proper testing and debugging of functionalities, and does not allow co-designing the accelerator to obtain a balanced and efficient architecture. Furthermore, since the popularization of multiprocessors in the last few decades, which currently offer up to hundreds of cores per chip, it has become the norm to parallelize any software to obtain the maximum performance. However, if we look into the software tools needed to develop hardware, e.g., RTL simulators, we only see little adoption of parallel techniques, typically constrained to a single node and a few threads.
The NECSTLab is a DEIB laboratory, with different research lines on advanced topics in computing systems: from architectural characteristics, to hardware-software codesign methodologies, to security and dependability issues of complex system architectures.
Every week, the “NECSTFridayTalk” invites researchers, professionals or entrepreneurs to share their work experiences and projects they are implementing in the “Computing Systems”.
