NECSTFridayTalk – MARCH: Multi-staging Array Compiler for High-Level Synthesis
Speaker: Francesco Peverelli
PHD Student in Information Technology
DEIB - NECSTLab Meeting Room (Bld. 20)
Online by Zoom
November 8h, 2024 | 11.30 am
Contact: Prof. Marco Santambrogio
PHD Student in Information Technology
DEIB - NECSTLab Meeting Room (Bld. 20)
Online by Zoom
November 8h, 2024 | 11.30 am
Contact: Prof. Marco Santambrogio
Sommario
On November 8th, 2024 at 11.30 am a new appointment of NECSTFridayTalk series titled "MARCH: Multi-staging Array Compiler for High-Level Synthesis" will take place at DEIB NECSTLab Meeting Room (Building 20) and on line by Zoom.
During this first talk, we will have, as speaker, Francesco Peverelli, PhD at Dipartimento di Elettronica, Informazione e Bioingegneria.
The most straightforward way to implement a DSL is to embed it into a high-level language, such as C++ or Java, and leverage operator overloading. However, this approach has limitations, such as the extraction of control flow. The Buildit library solves this problem by introducing type-based multi-staging in C++, offering a new way to build DSL, which is lightweight and requires less cumbersome compiler code writing. In today's talk, we present MARCH, a Buildit-based DSL and compiler targeting the AMD High-Level Synthesis toolchain. MARCH explores how multi-staging can be leveraged at several stages in the compilation pipeline to build complex dataflow analyses targeting reconfigurable hardware. We show how the MARCH DSL and scheduling co-language can be used to succinctly express complex code transformations related to HLS design.
During this first talk, we will have, as speaker, Francesco Peverelli, PhD at Dipartimento di Elettronica, Informazione e Bioingegneria.
The most straightforward way to implement a DSL is to embed it into a high-level language, such as C++ or Java, and leverage operator overloading. However, this approach has limitations, such as the extraction of control flow. The Buildit library solves this problem by introducing type-based multi-staging in C++, offering a new way to build DSL, which is lightweight and requires less cumbersome compiler code writing. In today's talk, we present MARCH, a Buildit-based DSL and compiler targeting the AMD High-Level Synthesis toolchain. MARCH explores how multi-staging can be leveraged at several stages in the compilation pipeline to build complex dataflow analyses targeting reconfigurable hardware. We show how the MARCH DSL and scheduling co-language can be used to succinctly express complex code transformations related to HLS design.
The NECSTLab is a DEIB laboratory, with different research lines on advanced topics in computing systems: from architectural characteristics, to hardware-software codesign methodologies, to security and dependability issues of complex system architectures.
Every week, the “NECSTFridayTalk” invites researchers, professionals or entrepreneurs to share their work experiences and projects they are implementing in the “Computing Systems”.
