ML for EDA: Myth or Reality?
Prof. Siddharth Garg
New York University
DEIB - PT1 Room (Building 20)
June 29th, 2023
11.30 am
Contacts:
Christian Pilato
Research Line:
System architectures
New York University
DEIB - PT1 Room (Building 20)
June 29th, 2023
11.30 am
Contacts:
Christian Pilato
Research Line:
System architectures
Sommario
On June 29th, 2023 at 11.30 am Siddharth Garg, Professor at New York University, will give a seminar on "ML for EDA: Myth or Reality?" in DEIB PT1 Room (Building 20).
There has been a lot of recent buzz around a new generation of EDA/CAD tools based on machine learning. Is this hype warranted? In this talk, I will discuss the why, what, and how of ML for EDA using two problems as case studies:
(1) large language model-based automatic Verilog code generation from natural language specifications; and (2) reinforcement learning for logic synthesis. I will highlight encouraging preliminary results that demonstrate the massive potential to substantially improve design quality and/or time-to-market, as well as roadblocks to achieving this potential including the (non)-availabilty of large and high-quality datasets. To this end, I will describe our experience curating two large-scale, high-quality datasets for Verilog code generation and logic synthesis. The first, Verigen, is a dataset of Verilog code collected from GitHub and Verilog textbooks. The second, OpenABC-D, is a large-scale, labeled dataset designed to aid ML for logic synthesis tasks. The dataset consists of 870,000 And-Inverter-Graphs (AIGs) produced from 1500 synthesis runs on a large number of open-source hardware projects. I will conclude with some directions for future research.
There has been a lot of recent buzz around a new generation of EDA/CAD tools based on machine learning. Is this hype warranted? In this talk, I will discuss the why, what, and how of ML for EDA using two problems as case studies:
(1) large language model-based automatic Verilog code generation from natural language specifications; and (2) reinforcement learning for logic synthesis. I will highlight encouraging preliminary results that demonstrate the massive potential to substantially improve design quality and/or time-to-market, as well as roadblocks to achieving this potential including the (non)-availabilty of large and high-quality datasets. To this end, I will describe our experience curating two large-scale, high-quality datasets for Verilog code generation and logic synthesis. The first, Verigen, is a dataset of Verilog code collected from GitHub and Verilog textbooks. The second, OpenABC-D, is a large-scale, labeled dataset designed to aid ML for logic synthesis tasks. The dataset consists of 870,000 And-Inverter-Graphs (AIGs) produced from 1500 synthesis runs on a large number of open-source hardware projects. I will conclude with some directions for future research.
Biografia
Siddharth is currently an Institute Associate Professor of ECE at NYU. He received his Ph.D. degree in Electrical and Computer Engineering from Carnegie Mellon University in 2009, and a B.Tech. degree in Electrical Engineering from the Indian Institute of Technology Madras.
He joined NYU in Fall 2014 as an Assistant Professor, and prior to that, was an Assistant Professor at the University of Waterloo from 2010-2014. His research interests are in machine learning, cyber-security, and computer hardware design. He is a member of NYU Center for Cybersecurity and NYU WIRELESS. In 2016, Siddharth was listed in Popular Science Magazine’s annual list of “Brilliant 10” researchers. Siddharth has received the NSF CAREER Award (2015), best paper awards at the IEEE Symposium on Security and Privacy (S&P) 2016 and the USENIX Security Symposium 2013. His NDSS 2015 paper was selected as a “Top Picks” in Hardware Security in 2019. Siddharth also received the Angel G. Jordan Award from ECE department of Carnegie Mellon University for outstanding thesis contributions and service to the community. He serves on the technical program committee of several top conferences in the area of computer engineering and computer hardware and has served as a reviewer for several IEEE and ACM journals.
He joined NYU in Fall 2014 as an Assistant Professor, and prior to that, was an Assistant Professor at the University of Waterloo from 2010-2014. His research interests are in machine learning, cyber-security, and computer hardware design. He is a member of NYU Center for Cybersecurity and NYU WIRELESS. In 2016, Siddharth was listed in Popular Science Magazine’s annual list of “Brilliant 10” researchers. Siddharth has received the NSF CAREER Award (2015), best paper awards at the IEEE Symposium on Security and Privacy (S&P) 2016 and the USENIX Security Symposium 2013. His NDSS 2015 paper was selected as a “Top Picks” in Hardware Security in 2019. Siddharth also received the Angel G. Jordan Award from ECE department of Carnegie Mellon University for outstanding thesis contributions and service to the community. He serves on the technical program committee of several top conferences in the area of computer engineering and computer hardware and has served as a reviewer for several IEEE and ACM journals.
