Computing With or Without Interconnects - A Performance and Security Perspective
Prof. Amlan Ganguly
Rochester Institute of Technology
New York, USA
DEIB - PT1 Room (Building 20)
March 22nd, 2023
9.30 am
Contacts:
William Fornaciari
Research Line:
System architectures
Rochester Institute of Technology
New York, USA
DEIB - PT1 Room (Building 20)
March 22nd, 2023
9.30 am
Contacts:
William Fornaciari
Research Line:
System architectures
Sommario
On March 22nd, 2023 at 9.30 am Amlan Ganguly, Professor & Department Head, Computer Engineering Rochester Institute of Technology, New York, will give a seminar on "Computing With or Without Interconnects. A Performance and Security Perspective" in DEIB PT1 Room.
Compute-intensive platforms such as micro-servers and embedded systems have already undergone a shift from a single-chip to multichip architecture to achieve better yield and scalable computational capacity. However, performance of multichip systems with multiple chiplets or dielets is limited by the latency and power-hungry chip-to-chip wired I/Os. Moreover, with the increase in memory-intensive applications and hence one-to-many traffic in a multichip system, this scenario gets even worse as conventionally one-to-many traffic is handled as multiple unicast traffic in a traditional interconnection infrastructure.
On the other hand, wireless interconnections overlaid on silicon interposers have been demonstrated to be energy-efficient and low latency interconnect solution for such multichip systems as it can mask long multi-hop off-chip wired I/O communication and provide support for one-to-many traffic needs. Despite efficient communication, the unguided on and off-chip wireless communication introduce security vulnerabilities in the system. In this talk, we discuss a low-latency, reconfigurable and secure interconnection architecture for multichip systems capable of detecting and defending against emerging threats including Hardware Trojans (HTs) and Denial-of-Service (DoS) using a Machine Learning (ML)-based approach. The ML-based approach is used to classify attack scenarios to enable the required defense mechanism. Due to the various challenges of interconnects related to the “memory-wall” and security we also investigate a novel approach for in-memory computing that eliminates the need for interconnects. Processing in memory (PIM) architecture, with its ability to perform ultra-low-latency parallel processing, is regarded as a more suitable alternative to von Neumann computing architectures for implementing data-intensive applications such as Deep Learning or Data Encryption. In this talk, we present a Look-up Table (LUT) based PIM architecture aimed at CNN/DNN acceleration that replaces logic-based processing with pre-calculated results stored inside the memory in order to perform complex computations on the DRAM memory platform. The talk concludes with some other related ongoing projects and our vision on future research directions along these threads.
Compute-intensive platforms such as micro-servers and embedded systems have already undergone a shift from a single-chip to multichip architecture to achieve better yield and scalable computational capacity. However, performance of multichip systems with multiple chiplets or dielets is limited by the latency and power-hungry chip-to-chip wired I/Os. Moreover, with the increase in memory-intensive applications and hence one-to-many traffic in a multichip system, this scenario gets even worse as conventionally one-to-many traffic is handled as multiple unicast traffic in a traditional interconnection infrastructure.
On the other hand, wireless interconnections overlaid on silicon interposers have been demonstrated to be energy-efficient and low latency interconnect solution for such multichip systems as it can mask long multi-hop off-chip wired I/O communication and provide support for one-to-many traffic needs. Despite efficient communication, the unguided on and off-chip wireless communication introduce security vulnerabilities in the system. In this talk, we discuss a low-latency, reconfigurable and secure interconnection architecture for multichip systems capable of detecting and defending against emerging threats including Hardware Trojans (HTs) and Denial-of-Service (DoS) using a Machine Learning (ML)-based approach. The ML-based approach is used to classify attack scenarios to enable the required defense mechanism. Due to the various challenges of interconnects related to the “memory-wall” and security we also investigate a novel approach for in-memory computing that eliminates the need for interconnects. Processing in memory (PIM) architecture, with its ability to perform ultra-low-latency parallel processing, is regarded as a more suitable alternative to von Neumann computing architectures for implementing data-intensive applications such as Deep Learning or Data Encryption. In this talk, we present a Look-up Table (LUT) based PIM architecture aimed at CNN/DNN acceleration that replaces logic-based processing with pre-calculated results stored inside the memory in order to perform complex computations on the DRAM memory platform. The talk concludes with some other related ongoing projects and our vision on future research directions along these threads.
Biografia
Amlan Ganguly is Professor and Department Head of Computer Engineering at Rochester Institute of Technology and Director (Planning) of the NSF Industry-University Co-operative Research Center on Smart Spaces Research (CSSR). Dr. Ganguly received his Bachelor of Technology from Indian Institute of Technology, Kharagpur and MS and PhD from Washington State University. His research interests are in interconnection networks for multi/many-core chips, data centers, non-von Neumann architectures, their security and sustainability. He has published over a hundred peer-reviewed articles and received four best paper awards and nominations. His teaching interests are in digital systems, multicore chips, interconnection networks and hardware security. He received the NSF Early CAREER Development Program Award in 2015. He is a senior member of IEEE.
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