Research Projects
Research Projects

Quantum Key Distribution High-Rate Detector Pre-development (4S SAGA)

Research Area:

Responsible:

Collaboration with Academic Institutions and Research Centres

DEIB Role: Coordinator

Length: 24 months

Start date: 2023-03-01

Project abstract

The Quantum Key Distribution High-Rate Detector Pre-Development project, carried out in collaboration with the European Space Agency (ESA) has the following objectives:

  1. Developing a ground-based single-photon receiver prototype with a high photon rate and high quantum efficiency in the 800 nm spectral band and its associated QKD (Quantum Key Distribution) detection systems to significantly increase the QKD secret key rate.
  2. Manufacturing and testing of the single-photon receiver demonstrator with a QKD system demonstrating the QKD key rate benefit by teaming-up (if it’s required) with a laboratory with an appropriate measurement set-up.
The main target improvement of this activity is the achievement of high secret key rates with faint pulse source based QKD systems to optimize the cost per key volume. Currently, the limiting factor in space to ground QKD distribution systems is the bandwidth of the single photon detector on ground, limiting the maximum repetition rate of the space-based sources. Within this activity the detector time resolution shall be improved to increase the detection at the level of GHz rate. This activity will mainly focus on the development of a ground-based receiver. Still, the feasibility of a space qualify detector shall also be covered in a technical trade-off. It might be assessed for a follow-up SAGA activity addressing monitoring of the quantum parameters of the QKD transmitter.

In detail, the Department of Electronics, Information and Bioengineering - Politecnico di Milano will design, fabricate and test a novel high-rate single photon detector integrated circuit. The single-photon detector will be a SPAD (single-photon avalanche diode) array and it is planned to be developed in a 3D stacked CMOS technology, combining a scaled logic tier, an imaging optimized SPAD tier and a third tier consisting of microlenses. As an alternative and more conservative approach, a planar CMOS SPAD array will be developed in parallel, where both the detectors and the electronics are in the same layer, with the disadvantage of lower collection efficiency.

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