High reliability fault tolerant digital systems in nanometric technologies: characterization and design methodologies

Project abstract

This project aims at the investigation of methods and tools for the design of reliable systems onto complex platforms, following the System on Programmable Chip (SoPC) paradigm, against both transient and permanent faults. The final goal is to design systems suitable for the automotive and avionics environments.
More precisely, research units will investigate:

• fault models specifically suited for the adopted platform and device
• techniques and methods for hardening the system being designed, in both its programmable and fixed components, tackling also the processor architecture, and
• achieved fault management analysis, through both simulated and in field fault injection campaigns.

The units background and competences will be integrated in order to define a set of methodologies for both designing and analyzing a hardened SoPC. An additional goal of the project is the definition of an architectural solution to be easily adopted and employed in critical application scenarios. The industrial producers of programmable devices have shown their interest in the development of solutions to harden their products, which then can directly be adopted for developing systems targeted for critical environments, characterized by high reliability requirements. The interaction with companies interested in the project will allow the identification of real application scenarios, to exploit the benefits of the proposed innovative solutions, providing a significant feedback for future improvements.

Project results

The results of the research project in terms of methodologies and architectural solutions are of interest for both users, since they allow the realization of fault tolerant systems using commercial devices and standard architectures, and for Silicon foundries, since the proposed architectural solutions could be of interest for the design of integrated circuits realized with the last generation technologies which will be prone to a very high number of Soft Errors. The project thus will provide innovative technical solutions to achieve the necessary level of fault tolerance, foreseeing the adoption of this kind of systems in critical application environment as well as in today’s pervasive contexts. The project will also provide means to disseminate the know-how of the research units on the issue of reliable design methodologies.

Publications:

• C. Bolchini, A. Miele, C. Sandionigi, N. Battezzati, L. Sterpone, M. Violante, “An integrated flow for the design of hardened circuits on SRAM-based FPGAs,” Proc. IEEE European Test Symposium - ETS, pp. 214-219, 2010.
• C. Bolchini, P. Luca Lanzi and A. Miele, “A MultiObjective Genetic Algorithm Framework for Design Space Exploration of Reliable FPGA based Systems,” in Proc. IEEE World Congress on Computational Intelligence - CEC, pp. 419-426, 2010.